1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, to an improvement of the wiring structure of a semiconductor device.
2. Description of the Related Art
As the integration density of a semiconductor device has been increased in recent years, a wiring layer has been decreased in thickness and width, and a multilayered wiring structure has been developed. As a conventional wiring material, Al has been used. However, even when the sectional area of a wiring layer is decreased by miniaturizing a device, a signal current is not reduced. For this reason, a current density is increased, and disconnection caused by electromigration poses a problem. In addition, in a multilayered structure requiring a large number of annealing processes, since a wiring layer receives complex heat hysteresis, disconnection caused by stress migration generated by heat stress acting on the wiring layer poses a problem.
As a next generation wiring material having an electrical resistance lower than that of Al and a high resistance to electromigration and stress migration, Cu and Ag begin to be considered. However, Cu is easily oxidized, and Cu is internally oxidized even at a low temperature, i.e., about 200.degree. C. Since this oxidation causes an increase in resistance, it must be prevented.
In order to realize this, a method of protecting the surface of Cu with a protective film is proposed (Jpn. Pat. Appln. KOKAI Publication No. 63-156341). This technique will be described below with reference to FIGS. 1A to 1C.
As shown in FIG. 1A, an SiO.sub.2 film 2 is formed on a silicon substrate 1, and a multilayered film constituted by a Ti film 3, a TiN film 4, a Cu film 5, and a TiN film 6 is formed on the SiO.sub.2 film 2.
As shown in FIG. 1B, a TiN film 7 is deposited on the entire surface of the resultant structure such that the side surfaces of the multilayered film are covered with the TiN film 7.
Finally, as shown in FIG. 1C, the TiN film 7 on a portion except for the side surfaces of the multilayered film is selectively removed, so as to obtain a Cu wiring layer having a structure in which the Cu film 5 is covered with the TiN films 6 and 7.
However, this method cannot be easily, practically used because the method is complicated and requires a large number of processes.
As another method of forming a Cu wiring layer which is obtained by covering a Cu film with a protective film, a method using annealing is proposed (Jpn. Pat. Appln. KOKAI Publication No. 64-59938). This technique will be described below with reference to FIGS. 2A to 2C.
As shown in FIG. 2A, a diffusion barrier metal film 12 and a Cu--Ti alloy film 13 are sequentially deposited on an insulating film 11.
As shown in FIG. 2B, the diffusion barrier metal film 12 and the Cu--Ti alloy film 13 are patterned in a wiring form.
Finally, as shown in FIG. 2C, the resultant structure is annealed in a gas atmosphere containing N to diffuse Ti in the Cu--Ti alloy film 13 into the upper and side surfaces of the Cu--Ti alloy film 13 and to make the Cu--Ti alloy film 13 into a TiN film 14 and a Cu wiring layer 15 which serve as a protective film and as a wiring layer, respectively.
However, when the TiN film 14 is actually formed using this method, an annealing temperature must be set to be high to obtain the Cu wiring layer 15 having a low resistance, an impurity in the diffusion layer of a device is diffused again, and the device is degraded. When the annealing temperature is set to be low, Ti is left in the Cu wiring layer 15, and a wiring resistance is disadvantageously increased. In addition, when Ag is heated to about 70.degree. C. or more in the air, it is easily aggregated. Therefore, almost no consideration has been made for Ag as a practical wiring material.
On the other hand, the integration density of a semiconductor device is increased, a wiring structure for connecting devices to each other is complicated, and each wiring layer is decreased in size. Conventionally, a metal is deposited on an insulating film deposited on a semiconductor substrate, and is processed to form a wiring layer, and an insulating film is deposited on the resultant structure so as to be flattened. However, as a wiring structure is micropatterned, processing of a metal and flattening of an insulating film cannot be easily performed. In addition, a void is disadvantageously formed in a narrow region of the insulating film between metal wiring layers.
As disclosed in Jpn. Pat. Appln. KOKAI Publication No. 63-244858, since an insulating film is etched easier than a metal and has a melting point higher than that of the metal, the following method is examined. That is, a groove is formed in the insulating film by reactive ion etching, and a fluidized metal is buried into the groove.
In addition, a method of forming a metal wiring layer by selective growth using a seed layer is known. This method will be described below with reference to FIGS. 3A to 3H.
As shown in FIG. 3A, an SiO.sub.2 film 22 is deposited on a semiconductor substrate 21, a thin film 23 serving as a seed layer for selective growth is formed, and a resist pattern 24 is formed by a photolithographic technique. As shown in FIG. 3B, the thin film 23 is selectively etched using the resist pattern 24 as a mask. Thereafter, as shown in FIG. 3C, the resist pattern 24 is removed to obtain a pattern 23 serving as the seed layer.
As shown in FIG. 3D, an SiO.sub.2 film 25 is deposited on the entire surface of the resultant structure, and as shown in FIG. 3E, resist patterns 26 are formed by a photolithographic process so as to be aligned with the position of the seed layer 23 under the SiO.sub.2 film 25. At this time, in consideration of an alignment error, the resist patterns 26 must be formed such that the interval therebetween is smaller than the width of the seed layer 23.
As shown in FIG. 3F, the SiO.sub.2 film 25 is etched by RIE using the resist patterns 26 as masks. As shown in FIG. 3G, the resist patterns 26 are removed, and a groove for a wiring layer is left in the SiO.sub.2 film 25. Finally, as shown in FIG. 3H, a wiring material 27 is buried in the groove to form a wiring layer.
In the method shown in FIGS. 3A to 3H, the photographic process must be performed twice, and the process is complicated. In addition, since a larger seed layer must be formed in consideration of the alignment error between the seed layer and the resist pattern for forming the groove, micropatterning cannot be performed to the limit of photolithography.
As still another method, a method shown in FIGS. 4A to 4D is known. According to this method, as shown in FIG. 4A, an SiO.sub.2 film 28 is deposited on the entire surface in the state shown in FIG. 3B, and as shown in FIG. 4B, the SiO.sub.2 film 28 is polished using the resist pattern 24 as a stopper so as to be flattened. The resist pattern 24 is removed to form a groove for a wiring layer, and a wiring layer is formed on the seed layer by selective growth. According to this method, the shape of the patterned seed layer is formed to have a size smaller than that of the resist portion because of the following reason. That is, when palladium is used as the material of the seed layer, as shown in FIG. 3A, and etching is performed by a solution mixture of hydrochloric acid, nitric acid, and hydrogen peroxide, this etching progresses in a lateral direction using the resist pattern as a mask, thereby obtaining the shape shown in FIG. 4A. In addition, even when the resist pattern is formed by RIE, the shape described above is obtained by a deposit formed during etching. When a groove is formed in the structure having the above shape, the shape shown in FIG. 4C is obtained.
When selective growth is performed to the structure having the shape, a bottom portion having no seed layer is formed as shown in FIG. 4D, and cavities 29 are formed at the bottom portion. In addition, even when the cavities are buried with a wiring material, a large stress acts in lateral and vertical directions, cracks 30 occur, and the reliability of an element is degraded by the excessive stress.